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Taiwan Semiconductor Research Institute

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Chip Implementation
  • Chip Implementation
    • Service Descriptions
    • Tape-out Schedule
    • Tape-out Guidelines
    • Tape-out Application
    • Test Report
    • Total Credit
    • FAQ
    • Tape-out Approval
    • Full-price Packaging/Back-end Dicing
    • Contact
    • Price List
  • Process/Silicon Intellectual Property(SIP)
    • Process/SIP Introduction
    • Process/SIP Application
    • Legal Literacy Advocacy Test
    • Technical Data Download
    • Online Assessment of Information Security
    • Service Lab
  • PCB/IPD/Flip Chip Implementation
    • PCB Process/Schedule/Contact
    • PCB Software/Technical Data
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    • PCB Post-application Operation
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    • Full-price Flip-chip Assembly Fabrication
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Home Chip ImplementationChip ImplementationFull-price Packaging/Back-end Dicing
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Full-price Packaging/Back-end Dicing

Application for Full-price Packaging/Dicing

For Full-price Dicing or Full-price Packaging, no process data authorization is required. The applicant can proceed with the service application after becoming a member of TSRI.
Before applying, please read the application instructions and required documents below.

Required Documents



Application Item Instructions and Details Reference Form Required Documents Pricing Policy
Full-price Dicing
  • Before proceeding, please verify the feasibility with the designated contact person. If feasible:
  • Please download the "Waiver of Liability for Chip Dicing and Packaging" form, complete it with your signature, and upload the signed form when filling out the online application form.
  • Please provide the cutting diagram and upload it when filling out the online application form.
  • Waiver of Liability for Chip Dicing and Packaging
1.Cutting Diagram
2.Wafers or Dies
The quotes will vary depending on the dicing method. For more details, please get in touch with the designated contact person.
Full-price Packaging
  • The minimum quantity for a single application is 8 chips, with no maximum limit.
  • Please download the "Waiver of Liability for Chip Dicing and Packaging" form, complete it with your signature, and upload the signed form when filling out the online application form.
  • Please provide the wire-bonding diagram and upload it when filling out the online application form.
  • Wire Bonding Diagram Template Download
  • Wire-Bonding Diagram Examples
  • Waiver of Liability for Chip Dicing and Packaging
1.Wire-Bonding Diagram
2.Dies
Please refer to Chip Implementation > Price List.


Shipping of Items

Mailing Address: No. 26, Prosperity Road I, Hsinchu Science Park, Hsinchu City 300091, Taiwan (Attn: Customer Service Team, TSRI)


Contact

For inquiries, please contact Ms. Fang-Lin Hsu; Ext. 7123
Email:fanglin@niar.org.tw
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Customer Service:tsri-cs@niar.org.tw ext:7610
  • Hsinchu Base
    No.26, Prosperity Road I, Hsinchu Science Park, Hsinchu 300091, Taiwan, R.O.C.
    TEL. +886-3-5773693FAX. +886-3-5713403
  • Tainan Base
    No.25, Xiaodong Road, Tainan City 704017, Taiwan, R.O.C.
    TEL. +886-6-2090160FAX. +886-6-2086669
  • NCKU Chimei Office
    7F, Chimei Building, Tzu-Chiang Campus, No.1, University Road, Tainan City 701401, Taiwan, R.O.C.
    TEL. +886-6-2087971FAX. +886-6-2089122
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